Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The process of manufacturing integrated circuits typically consists of many steps, during which hundreds or thousands of copies of an integrated circuit can be formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure containing conductive material(s) is created, that can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow through the channel defined under the gate structure and between a source and drain region within the transistor. The source and drain regions and/or an upper portion of the gate structure facilitate this conductance by virtue of containing a majority of positively charged (P) or negatively charged (N) dopant materials. Adjusting the voltage applied to the gate changes the amount of current flowing through the channel. A gate electrode of the gate structure is separated from the channel by a gate dielectric, which is an insulator and which opposes current flow between the gate electrode and channel, such that the device does not conduct current until a sufficient voltage (at least as large as a threshold voltage Vt) is applied to the gate electrode.
Issues may persist with shrinking semiconductor devices. For example, random dopant fluctuation, and associated disadvantageous effects resulting therefrom, may become more prevalent as transistor widths and lengths are reduced. In general, random dopant fluctuation refers to differences in the amount of dopant atoms received within certain areas (e.g., source/drain regions and/or upper portion of gate structure) as those areas are reduced in size. For example, even the most uniform application of dopant atoms may produce a difference of a few atoms within targeted areas where the respective sizes of those areas are so small that they can only be expected to accommodate about one hundred or fewer dopant atoms. In such small areas, a difference of just a few dopant atoms can cause the areas to have different electrical properties. This can, for example, cause respective transistors which are formed from one or more of these areas to have different operating characteristics. For example, a plurality of transistors that are supposed to be ‘matched’ may trigger on or off at different threshold voltages (Vt). It can be appreciated that the effects of RDF may be even more noticeable in certain types of semiconductor devices, such as static random access memory (SRAM), for example, which incorporate multiple transistors.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMS) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed. DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Thus, SRAMs are generally more reliable and operate faster than DRAMs. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback in the form of cross-coupled inverters to store a bit of information, and the cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations. The basic CMOS SRAM cell generally includes two N-type (NMOS) pull-down or drive transistors and two P-type (PMOS) load transistors in a cross-coupled inverter configuration, with two additional NMOS select transistors added to make up a six-transistor cell. Additionally, application specific SRAM cells can include an even greater number of transistors. Since a plurality of transistors are utilized in SRAM, and since random dopant fluctuations may become more prevalent as transistor widths are reduced, the adverse effects of random dopant fluctuations may present themselves to a great degree in SRAM, particularly as that type of memory is continually scaled down.
Accordingly, it would be desirable to have a technique that would allow transistors to be scaled down while mitigating RDF, particularly where the transistors may be used in SRAM.